entity productReg_tb is
end entity;

architecture TESTBENCH of productReg_tb is

component productReg is
	port (
		H_in, L_in : in bit_vector(31 downto 0);
		clk, clr, load, hold : in bit;
		H_out, L_out : out bit_vector(31 downto 0);
		a_1 : out bit
	);
end component;

for all : productReg use entity work.productReg(STRUCTURAL);

signal high_input, low_input, high_output, low_output : bit_vector (31 downto 0);
signal clock, clear, load, hold, a_1 : bit;

begin

SR64 : productReg port map (high_input, low_input, clock, clear, load, hold, high_output, low_output, a_1);

high_input <= "01010101010101010101010101010101";
low_input <= "00000000000000000000000000000000";
load <= '1', '0' after 220 ns;
hold <= '0', '1' after 900 ns, '0' after 1100 ns;
clear <= '1' after 9000 ns;

PROCESS(clock)
	begin
	clock <= not clock after 50 ns; 
end PROCESS;

end architecture TESTBENCH;